Wichit Sirichote, email@example.com
Smaller but more powerful, the new C186SBC built with 16-bit Intel Embedded Microprocessor, 80C186EB.
My latest design for 16-bit single board computer, the C186SBC. The board features 16-bit data bus x86 compatible cpu and two serial ports: the RS232 for program debugging and RS485 for I/O boards networking. The CPU is 80C186EB, Intel embedded microprocessor. My first design, the C188SBC has rich of peripherals, the C186SBC instead has only RS485 port and small number of GPIO lines. My intention is to have the slave board made by a given microcontroller to be I/O devices. They will communicate with C186 via half-duplex RS485. The C186 as the central unit will be computing unit. Raws signal would be acquired by a front-end circuit, then received by C186. After making data reduction, the result will send back to the display unit.
Figure 1: The prototype of C186SBC V1.0
The C186SBC V1.0 features,
- CPU: 80C186EB 16MHz
- MEMORY: 29C010x2, 128kBx2 even and odd Flash
- 628128x2, 128kBx2 even and odd SRAM
- MEMORY and I/O Decoder: GAL16V8D
- Debug LED: single dot LED connected to P1.7
- Host terminal interface: RS232 9600 8n1
- I/O processors interface: half-duplex RS485
- Expansion connectors: 8-bit buffered cpu bus for peripheral interface and GPIO
- Monitor Program: x86Bug V1.0
Figure 2 shows complete hardware schematic of the C186SBC V1.0. The CPU is 80C186EB25, 68-pin PLCC package. The chip has internal oscillator. We use a 16MHz XTAL connected to CLKIN and OSCOUT pins. TP1 provides CLKOUT signal for peripheral. TP2 also provides active high reset signal. The CPU has 20-bit address lines. U2, U5 and U9 latch 20-bit A0-A19 for memory interface. U3 and U7 are 128kB SRAM. Each chip has A0-A16. U3 is for lower byte, D0-D7 and U7 for higher byte, D8-D15. Both chip are active with the same chip select signal, LCS (Low Chip Select). The LCS is programmed to select lower memory range for RAM. U4 and U8 are 128kB Flash memory, similar to SRAM, U4 is for even byte and U8 for odd byte. Both chips are selected by UCS (Upper Chip Select) signal. Reset vector is placed in high address at physical location 0xFFFF0. U10, the PLD decodes signal for low and high byte write cycle. The LS0-LS3 also used for memory and I/O read/write cycle. U1, 8-bit transceiver is enabled with GCS6 by signal EXP_DEN at pin 18 of PLD. UART0 is used for terminal interface with standard RS232. The signal level is converted by U13, MAX232. UART1 from GPIO port2 is for RS485 port. The direction is controlled by P1.0.
Figure 2: Complete hardware schematic, CPU, memory, PLD
Figure 3: Memory Map
The monitor program is the same as C188SBC with a bit modification for chip selects address range. You may learn commands from C188SBC page. The monitor x86Bug also provides boot loader feature, after load the code, you can press reset button onboard, it will jump from monitor to address 0x400. Since the C186 has no SW4 to force back to run monitor, we can power down the board to make the byte at 0x400 change from 0xEA to random value. Howvere this C186 board was designed for applications that need the code to be placed in ROM, the bootloader may not useful.
For developer who want to modify the monitor source code, I will suggest how to make the ROM for C186 board below.
Figure 5: Binary image for ROM development.
We can develop applications program with the help of monitor program. After it works fine we can move the code to ROM. Since the board has no bettery backup, so to use it as a dedicated controller, it is better to put the code in ROM and varibles in RAM. The diagram shown in Figure 5 demonstrates procedure how to place your code in ROM. My description refers to monitor program development. You may adapt the method for applications program as well. Let's see the number shown in Figure 5 with explanation below.
1. Suppose we write the code that fits in 64kB. Then we need to generate the machine code in binary image file with size of 64kB.
2. We must split the 64kB image file into even and odd 32kB images. The even file contains byte for even address and odd file for odd address. For Motorola 68000, even byte is high address and odd byte is low address. I have been confused when I was developed 68000 board. I spent a couple of week try to put even ROM to low address as I thought even address should be low byte and odd ROM to high address. But nothing happen. Lukily on one night, I read the 68000 datasheet again. It showed different from Intel. So after I swapped them, it worked ok. I am not sure for newest microprocessor, will Motorola still uses the same as 68k chip. That was my story, now get back to x86.
3. The 32kB image files must then be loaded into the buffer memory of the PROM programmer. Suppose we are going to use 128kB flash, 29C010, say. The 32kB image will show in the lower address from 0x00000-0x07FFF.
4. Suppose we are developing the monitor program, as we know that the physical address for reset vector of 80C186 is 0xFFFF0. We must copy the first 32kB image into the high address, or last 32kB for a given ROM, here we try with 29C010, so the last 32kB will be from address 0x18000 to 0xFFFFF. Willem Epromer has such command to copy buffer memory.
Here is the sample code for startup at reset vector, look at machine code for each location first. Begin from location 0xFFF0,
Even bytes are: BA FF 00 EE 00 00,
Odd byts are: A4 B8 F0 EA FF F0.
FFF0 org 0FFF0h FFF0 BAA4FF MOV DX, UCSST ; POINT TO UMCS REGISTERFFF3 B800F0 MOV AX, 0F000h ; FFF6 EE OUT DX, AL ; I used AT29C010A, access time is 70ns!FFF7 EA00FF00F0 JMP FAR PTR start2,0F000H ; jump to start
Now see the buffer memory after the even file was moved from step 3 to 4.
We see that the first byte BA appeared at location 0x1FFF8 followed with FF, 00, EE, 00 and 00.
For odd bytes the first byte A4 appeared at location 0x1FFF8 followed with B8, C0, EA, E0 and F0.
From schematic we see that the address lines that tie to both flash are A1-A17, this makes the reset vector appeared in flash memory is 0x1FFF8. When placed both chips to the board, the physical address well be at 0xFFFF0. For each file, even and odd files, you can program the buffer memory to the Flash chip. Don't forget to label each flash for ODD and EVEN. U4 is for EVEN and U8 for ODD.
Schematic and layout:
U11 RS485 Transceiver, replace P2.2 with P1.0.
Schematic, AST layer c186.pdf c186ast.pdf x86Bug Monitor Program, source code and binary image for even and odd flash Boot86.asm boot86.evn boot86.odd sample Pacific c code that prints cosine value on screen Test.c Test.hex Equation and JEDEC file for GAL16V8D C186.eqn
29 Dec 2004
Recovered 17 December 2015